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512 kbit / 1 mbit 3.0 volt-only, serial flash memory with 25 mhz spi bus interface pmc fea tures ? single power supply operation - low voltage range: 2.7 v - 3.6 v ? memory organization - pm25lv512: 64k x 8 (512 kbit) - pm25lv010: 128k x 8 (1 mbit) cost effective sector/block architecture - uniform 4 kbyte sectors - uniform 32 kbyte blocks (8 sectors per block) - two blocks with 32 kbytes each (512 kbit) - four blocks with 32 kbytes each (1 mbit) - 128 pages per block serial peripheral interface (spi) compatible - supports spi modes 0 (0,0) and 3 (1,1) high performance read - 25 mhz clock rate (maximum) page mode for program operations - 256 bytes per page block write protection - the block protect (bp1, bp0) bits allow part or entire of the memory to be configured as read-only. hardware data protection - write protect (wp#) pin will inhibit write operations to the status register ? page program (up to 256 bytes) - typical 2 ms per page program time sector, block and chip erase - typical 40 ms sector/block/chip erase time single cycle reprogramming for status register - build-in erase before programming high product endurance - guarantee 100,000 program/erase cycles per single sector (preliminary) - minimum 20 years data retention industrial standard pin-out and package - 8-pin jedec soic - 8-contact wson - optional lead-free (pb-free) packages general description the pm25lv512/010 are 512 kbit/1 mbits 3.0 volt-only serial flash memories. these devices are designed to use a single low voltage, range from 2.7 volt to 3.6 volt, power supply to perform read, erase and program operations. the devices can be programmed in standard eprom programmers as well. the device is optimized for use in many commercial applications where low-power and low-voltage operation are essential. the pm25lv512/010 is enabled through the chip enable pin (ce#) and accessed via a 3-wire interface consisting of serial data input (sl), serial data output (so), and serial clock (sck). all write cycles are com- pletely self-timed. block write protection for top 1/4, top 1/2 or the entire memory array (1m) or entire memory array (512k) is enabled by programming the status register. separate write enable and write disable instructions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. programmable microelectronics corp. 1 issue date: december, 2003, rev: 1.3 pm25lv512 / pm25lv010 the pm25lv512/010 are manufactured on pmc?s advanced nonvolatile cmos technology, p-flash?. the de- vices are offered in 8-pin jedec soic and 8-contact wson packages with operation frequency up to 25 mhz.
2 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 pin descriptions l o b m y se p y tn o i t p i r c s e d # e ct u p n i r o f s e i r t i u c r i c l a n r e t n i s ' e c i v e d e h t s e t a v i t c a w o l s e o g # e c : e l b a n e p i h c o t n i s e h c t i w s d n a e c i v e d e h t s t c e l e s e d h g i h s e o g # e c . n o i t a r e p o e c i v e d t o n s i e c i v e d e h t n e h w . n o i t p m u s n o c r e w o p e h t e c u d e r o t e d o m y b d n a t s e h t d n a , ) l s ( n i p t u p n i l a i r e s e h t a i v d e t p e c c a e b t o n l l i w a t a d , d e t c e l e s . e t a t s e c n a d e p m i h g i h a n i n i a m e r l l i w ) o s ( n i p t u p t u o l a i r e s k c st u p n ik c o l c a t a d l a i r e s i st u p n it u p n i a t a d l a i r e s o st u p t u ot u p t u o a t a d l a i r e s d n gd n u o r g c c vy l p p u s r e w o p e c i v e d # p wt u p n i l l a , " 1 " s i t i b n e p w d n a w o l o t t h g u o r b n i p # p w e h t n e h w : t c e t o r p e t i r w . d e t i b i h n i e r a r e t s i g e r s u t a t s e h t o t s n o i t a r e p o e t i r w # d l o ht u p n i t u o h t i w e c i v e d r e t s a m e h t h t i w n o i t a c i n u m m o c l a i r e s e s u a p : d l o h . e c n e u q e s l a i r e s e h t g n i t t e s e r connection diagrams 8-pin soic 5 6 7 8 1 2 3 4 vcc hold# sck si so gnd wp# ce# 8-contact wson 5 6 7 8 1 2 3 4 vcc hold# sck si so gnd wp# ce# top view
3 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 product ordering informa tion pm25l vxxx -25 s c e temperature range c = commercial (0 c to +70 c) package type s = 8-pin soic (8s) q = 8-contact wson (8q) operating speed 25 mhz pmc device number pm25lv512 (512 kbit) pm25lv010 (1 mbit) r e b m u n t r a py c n e u q e r f g n i t a r e p o) z h m (e g a k c a pe g n a r e r u t a r e p m e t e c s 5 2 - 2 1 5 v l 5 2 m p 5 2 s 8 l a i c r e m m o c ) c 0 7 + o t c 0 ( c s 5 2 - 2 1 5 v l 5 2 m p e c q 5 2 - 2 1 5 v l 5 2 m p q 8 c q 5 2 - 2 1 5 v l 5 2 m p e c s 5 2 - 0 1 0 v l 5 2 m p 5 2 s 8 c s 5 2 - 0 1 0 v l 5 2 m p e c q 5 2 - 0 1 0 v l 5 2 m p q 8 c q 5 2 - 0 1 0 v l 5 2 m p environmental attribute e = lead-free (pb-free) package blank = standard package
4 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 block diagram high voltage generator control logic serial /parallel convert logic address latch & counter 2kbit page buffer status register memory array y-decoder x-decoder instruction decoder spi chip block diagram
5 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 pm25lv512/010 can be driven by a microcontroller on the spi bus as shown in figure 1. the serial communication term definitions are in the following section. master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the pm25lv512/010 always operates as a slave. transmitter/receiver: the pm25lv512/010 has separate pins designated for data transmission (so) and recep tion (sl). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with ce# going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the pm25lv512/010, and the serial output pin (so) will remain in a high impedance state until the falling edge of ce# is detected again. this will reinitialize the serial communication. serial interf ace description spi interface with (0, 0) or (1, 1) sdo sdi sck sck so si bus master cs3 cs2 cs1 ce# wp# hold# hold# hold# spi memory device spi memory device spi memory device note: 1. the write protect (wp#) and hold (hold#) signals should be driven, high or low as appropriate. sck so si sck so si ce# wp# ce# wp# figure 1. bus master and spi memory devices
6 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 spi modes these devices can be driven by microcontroller with its spi peripheral running in either of the two following modes: mode 0 = (0, 0) mode 3 = (1, 1) for these two modes, input data is latched in on the rising edge of serial clock (sck), and output data is available from the falling edge of serial clock (sck). the difference between the two modes, as shown in figure 2, is the clock polarity when the bus master is in stand-by mode and not transfering data: - clock remains at 0 (sck = 0) for mode 0 (0, 0) - clock remains at 1 (sck = 1) for mode 3 (1, 1) figure 2. spi modes sck sck si so mode 0 (0 0) mode 3 (1 1) serial interf ace description (continued)
7 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 e m a n n o i t c u r t s n it a m r o f n o i t c u r t s n ie d o c x e hn o i t a r e p o n e r w0 1 1 0 0 0 0 0h 6 0h c t a l e l b a n e e t i r w t e s i d r w0 0 1 0 0 0 0 0h 4 0h c t a l e l b a n e e t i r w t e s e r r s d r1 0 1 0 0 0 0 0h 5 0r e t s i g e r s u t a t s d a e r r s r w1 0 0 0 0 0 0 0h 1 0r e t s i g e r s u t a t s e t i r w d a e r1 1 0 0 0 0 0 0h 3 0y r a r r a y r o m e m m o r f a t a d d a e r d a e r _ t s a f1 1 0 1 0 0 0 0h b 0d e e p s r e h g i h t a y r o m e m m o r f a t a d d a e r g o r p _ g p0 1 0 0 0 0 0 0h 2 0y a r r a y r o m e m o t n i a t a d m a r g o r p e s a r e _ r o t c e s1 1 1 0 1 0 1 1h 7 dy a r r a y r o m e m n i r o t c e s e n o e s a r e e s a r e _ k c o l b0 0 0 1 1 0 1 1h 8 dy a r r a y r o m e m n i k c o l b e n o e s a r e e s a r e _ p i h c1 1 1 0 0 0 1 1h 7 cy a r r a y r o m e m e r i t n e e s a r e d i d r1 1 0 1 0 1 0 1h b ad i t c u d o r p d n a r e r u t c a f u n a m d a e r table 1. instruction set for the pm25lv512/010 device operation the pm25lv512/010 is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the pm25lv512/010 utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 1. all instructions, addresses, and data are transferred with the msb first and start with a high- to-low transition. write is defined as program and/or erase in this specification. the following commands, page program, sector erase, block erase, chip erase, and wrsr are write instructions for pm25lv512/010. n o i t a c i f i t n e d i t c u d o r pa t a d d i r e r u t c a f u n a mh d 9 : d i e c i v e d 2 1 5 v l 5 2 m ph b 7 0 1 0 v l 5 2 m ph c 7 table 2. product identification read product id (rdid): the rdid instruction allows the user to read the manufacturer and product id of the device. the instruction code is followed by three dummy bytes, each bit being latched-in on serial data input (si) during the rising edge of serial clock (sck). then the first manufacturer id (9dh) is shifted out on serial data output (so), followed by the device id (7bh = pm25lv512; 7ch = pm25lv010) and the second manufacturer id (7fh), each bit been shifted out during the falling edge of serial clock (sck).
8 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 t i bn o i t i n i f e d ) y d r ( 0 t i b . y d a e r s i e c i v e d e h t s e t a c i d n i 0 = 0 t i b s i e c i v e d e h t d n a s s e r g o r p n i s i e l c y c e t i r w e h t s e t a c i d n i 1 = 0 t i b . y s u b ) n e w ( 1 t i b . d e l b a n e e t i r w t o n s i e c i v e d e h t s e t a c i d n i 0 = 1 t i b . d e l b a n e e t i r w s i e c i v e d e h t s e t a c i d n i 1 = 1 t i b ) 0 p b ( 2 t i b. 5 e l b a t e e s ) 1 p b ( 3 t i b. 5 e l b a t e e s . e l c y c e t i r w l a n r e t n i n a n i t o n s i e c i v e d n e h w s 0 e r a 6 - 4 s t i b ) n e p w ( 7 t i b . ) # p w ( n i p t c e t o r p e t i r w f o n o i t c n u f e h t s k c o l b 0 = n e p w . ) # p w ( n i p t c e t o r p e t i r w e h t s e t a v i t c a 1 = n e p w . s l i a t e d r o f 6 e l b a t e e s . e l c y c e t i r w l a n r e t n i n a g n i r u d s 1 e r a 7 - 0 s t i b table 4. read status register bit definition write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protec- tion for the pm25lv010. the pm25lv010 is divided into four blocks where the top quarter (1/4), top half (1/2), or all of the memory blocks can be protected (locked out) from write. the pm25lv512 is divided into 2 blocks where all of the memory blocks can be protected (locked out) from write. any of the locked-out blocks will therefore be read only. the locked-out block and the corresponding status register control bits are shown in table 5. the three bits, bp0, bp1, and wpen, are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., wren, rdsr). write enable (wren): the device will power up in the write disable state when vcc is applied. all write instructions must therefore be preceded by the wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the wrdi instruction disables all write commands. the wrdi instruction is independent of the status of the wp# pin. read status register (rdsr): the rdsr instruction provides access to the status register. the ready/ busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. during internal write cycles, all other commands will be ignored except the rdsr instruction. 7 t i b6 t i b5 t i b4 t i b3 t i b2 t i b1 t i b0 t i b n e p w xxx 1 p b0 p bn e wy d r table 3. status register format
9 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 n e p wp wn e ws k c o l b d e t c e t o r ps k c o l b d e t c e t o r p n ur e t s i g e r s u t a t s 0x 0 d e t c e t o r pd e t c e t o r pd e t c e t o r p 0x 1 d e t c e t o r pe l b a t i r we l b a t i r w 1w o l0 d e t c e t o r pd e t c e t o r pd e t c e t o r p 1w o l1 d e t c e t o r pe l b a t i r wd e t c e t o r p xh g i h0 d e t c e t o r pd e t c e t o r pd e t c e t o r p xh g i h1 d e t c e t o r pe l b a t i r we l b a t i r w table 6. wpen operation the wrsr instruction also allows the user to enable or disable the write protect (wp#) pin through the use of the write protect enable (wpen) bit. hardware write protection is enabled when the wp# pin is low and the wpen bit is "1". hardware write protection is disabled when either the wp# pin is high or the wpen bit is "0." when the device is hardware write protected, writes to the status register, including the block protect bits and the wpen bit, and the locked-out blocks in the memory array are disabled. write is only allowed to blocks of the memory which are not locked out. the wrsr instruction is self-timed to automatically erase and program bp0, bp1, and wpen bits. in order to write the status register, the device must first be write enabled via the wren instruction. then, the instruction and data for the three bits are entered. during the internal write cycle, all instructions will be ignored except rdsr instructions. the pm25lv512/010 will automatically return to write disable state at the completion of the wrsr cycle. note: when the wpen bit is hardware write protected, it cannot be changed back to "0", as long as the wp# pin is held low. l e v e l s t i b r e t s i g e r s u t a t s2 1 5 v l 5 2 m p0 1 0 v l 5 2 m p 1 p b0 p b s e s s e r d d a y a r r a t u o d e k c o l t u o - d e k c o l ) s ( k c o l b s e s s e r d d a y a r r a t u o d e k c o l t u o - d e k c o l ) s ( k c o l b 000 e n o ne n o n e n o ne n o n ) 4 / 1 ( 101 f f f f 1 0 - 0 0 0 8 1 04 k c o l b ) 2 / 1 ( 210 f f f f 1 0 - 0 0 0 0 1 04 , 3 k c o l b ) l l a ( 311 f f f f 0 0 - 0 0 0 0 0 0 s k c o l b l l a ) 2 - 1 ( f f f f 1 0 - 0 0 0 0 0 0 s k c o l b l l a ) 4 - 1 ( table 5. block write protect bits
10 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 read: reading the pm25lv512/010 via the so (serial output) pin requires the following sequence. after the ce# line is pulled low to select a device, the read instruction is transmitted via the sl line followed by the byte address to be read (refer to table 7). upon completion, any data on the sl line will be ignored. the data (d7-d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the ce# line should be driven high after the data comes out. the read instruction can be continued since the byte address is automati- cally incremented and data will continue to be shifted out. for the pm25lv512/010, when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read instruction. fast_read: the device is first selected by driving ce# low. the fast read instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of sck (serial clock). then the memory contents, at that address, is shifted out on so (serial output), each bit being shifted out, at a maximum frequency f fr , during the falling edge of sck (serial clock). the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read with a single fast read instruction. the fast read instruction is terminated by driving ce# high. page program (pg_prog): in order to program the pm25lv512/010, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then the page program instruc- tion can be executed. also, the address of the memory location(s) to be programmed must be outside the pro- tected address field location selected by the block write protection level. during an internal self-timed program- ming cycle, all commands will be ignored except the rdsr instruction. the page program instruction requires the following sequence. after the ce# line is pulled low to select the device, the page program instruction is transmitted via the sl line followed by the address and the data (d7-d0) to be programmed (refer to table 7). programming will start after the ce# pin is brought high. the low-to-high transition of the ce# pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a rdsr instruction. if bit 0 = 1, the program cycle is still in progress. if bit 0=0, the program cycle has ended. only the rdsr instruction is enabled during the program cycle. a single program instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. the starting byte could be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. if more than 256 bytes of data are provided, the address counter will roll over on the same page and the previous data provided will be replaced. the same byte cannot be reprogrammed without erasing the whole sector/block first. the pm25lv512/010 will automatically return to the write disable state at the completion of the program cycle. note: if the device is not write enabled (wren) the device will ignore the write instruction and will return to the standby state, when ce# is brought high. a new ce# falling edge is required to re-initiate the serial communication. s s e r d d a2 1 5 v l 5 2 m p0 1 0 v l 5 2 m p a n a 5 1 a - 0 a 6 1 a - 0 s t i b e r a c t ' n o da 3 2 a - 6 1 a 3 2 a - 7 1 table 7. address key
11 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 s s e r d d a k c o l bk c o l b 2 1 5 v l 5 2 m pk c o l b 0 1 0 v l 5 2 m p f f f 7 0 0 o t 0 0 0 0 0 01 k c o l b1 k c o l b f f f f 0 0 o t 0 0 0 8 0 02 k c o l b2 k c o l b f f f 7 1 0 o t 0 0 0 0 1 0a / n3 k c o l b f f f f 1 0 o t 0 0 0 8 1 0a / n4 k c o l b table 8. block addresses sector_erase, block_erase: before a byte can be reprogrammed, the sector/block which contains the byte must be erased. in order to erase the pm25lv512/010, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then the sector erase or block erase instruction can be executed. the block erase instruction erases every byte in the selected block if the block is not locked out. block address is automatically determined if any address within the block is selected. the block erase instruction is internally controlled; it will automatically be timed to completion. during this time, all commands will be ignored, except rdsr instruction. the pm25lv512/010 will automatically return to the write disable state at the completion of the block erase cycle. chip_erase: as an alternative to the sector and block erase, the chip erase instruction will erase every byte in all blocks that are not locked out. first, the device must be write enabled via the wren instruction. then the chip erase instruction can be executed. the chip erase instruction is internally controlled; it will automatically be timed to completion. the chip erase cycle time maximum is 100 miliseconds. during the internal erase cycle, all instructions will be ignored except rdsr. the pm25lv512/010 will automatically return to the write disable state at the completion of the chip erase. hold: the hold# pin is used in conjunction with the ce# pin to select the pm25lv512/010. when the device is selected and a serial sequence is underway, hold# pin can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold# pin must be brought low while the sck pin is low. to resume serial communication, the hold# pin is brought high while the sck pin is low (sck may still toggle during hold). inputs to the sl pin will be ignored while the so pin is in the high impedance state. hardware write protect: the pm25lv512/010 has a write lockout feature that can be activated by assert- ing the write protect pin (wp#). when the lockout feature is activated, locked-out sectors will be read only. the write protect pin will allow normal read/write operations when held high. when the wp# is brought low and wpen bit is "1", all write operations to the status register are inhibited. wp# going low while ce# is still low will interrupt a write to the status register. if the internal status register write cycle has already been initiated, wp# going low will have no effect on any write operation to the status register. the wp# pin function is blocked when the wpen bit in the status register is "0". this will allow the user to install the pm25lv512/010 in a system with the wp# pin tied to ground and still be able to write to the status register. all wp# pin functions are enabled when the wpen bit is set to "1".
12 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 dc and ac opera ting range absolute maximum ra tings (1) notes: 1. stresses under those listed in ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. the functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. maximum dc voltage on input or i/o pins are v cc + 0.5 v. during voltage transitioning period, input or i/o pins may overshoot to v cc + 2.0 v for a period of time up to 20 ns. minimum dc voltage on input or i/o pins are -0.5 v. during voltage transitioning period, input or i/o pins may undershoot gnd to -2.0 v for a period of time up to 20 ns. s a i b r e d n u e r u t a r e p m e t c 5 2 1 + o t c 5 6 - e r u t a r e p m e t e g a r o t s c 5 2 1 + o t c 5 6 - e r u t a r e p m e t g n i r e d l o s d a e l t n u o m e c a f r u s e g a k c a p d r a d n a t ss d n o c e s 3 c 0 4 2 e g a k c a p e e r f - d a e ls d n o c e s 3 c 0 6 2 s n i p l l a n o d n u o r g o t t c e p s e r h t i w e g a t l o v t u p n i ) 2 ( v o t v 5 . 0 - c c v 5 . 0 + d n u o r g o t t c e p s e r h t i w e g a t l o v t u p t u o l l a v o t v 5 . 0 - c c v 5 . 0 + v c c ) 2 ( v 0 . 6 + o t v 5 . 0 - r e b m u n t r a p 0 1 0 / 2 1 5 v l 5 2 m p e r u t a r e p m e t g n i t a r e p o c 0 7 o t c 0 y l p p u s r e w o p c c v v 6 . 3 - v 7 . 2
13 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 dc characteristics applicable over recommended operating range from: t ac = 0 c to +70 c, v cc = +2.7 v to +3.6 v (unless otherwise noted). l o b m y sr e t e m a r a pn o i t i d n o cn i mp y tx a ms t i n u i 1 c c t n e r r u c d a e r e v i t c a c c vv c c n e p o = o s , z h m 5 2 t a v 6 . 3 =0 15 1a m i 2 c c t n e r r u c e s a r e / m a r g o r p c c vv c c n e p o = o s , z h m 5 2 t a v 6 . 3 =5 10 3a m i 1 b s s o m c t n e r r u c y b d n a t s c c vv c c v = # e c , v 6 . 3 = c c 1 . 05a i 2 b s l t t t n e r r u c y b d n a t s c c vv c c v = # e c , v 6 . 3 = h i v o t c c 5 0 . 03a m i i l t n e r r u c e g a k a e l t u p n iv n i v o t v 0 = c c 1a i o l t n e r r u c e g a k a e l t u p t u ov n i v o t v 0 = c c t , c a c 0 7 o t c 0 =1a v l i e g a t l o v w o l t u p n i5 . 0 -8 . 0v v h i e g a t l o v h g i h t u p n iv 7 . 0 c c v c c 3 . 0 +v v l o e g a t l o v w o l t u p t u o v 6 . 3 < c c v < v 7 . 2 i l o a m 1 . 2 =5 4 . 0v v h o e g a t l o v h g i h t u p t u oi h o a 0 0 1 - =v c c 2 . 0 -v
14 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 l o b m y sr e t e m a r a pn i mp y tx a ms t i n u f r f r o f y c n e u q e r f k c o l c d a e r _ t s a f 05 2z h m f r s n o i t c u r t s n i d a e r r o f y c n e u q e r f k c o l c00 2z h m t i r e m i t e s i r t u p n i 0 2s n t i f e m i t l l a f t u p n i 0 2s n t h k c e m i t h g i h k c s0 2s n t l k c e m i t w o l k c s0 2s n t h e c e m i t h g i h e c5 2s n t s c e m i t p u t e s e c5 2s n t h c e m i t d l o h e c5 2s n t s d e m i t p u t e s n i a t a d5s n t h d e m i t d l o h n i a t a d5s n t s h e m i t p u t e s d l o h5 1s n t d h e m i t d l o h5 1s n t v d i l a v t u p t u o 5 1s n t h o e m i t d l o h t u p t u o0s n t z l z w o l t u p t u o o t d l o h 0 0 2s n t z h z h g i h t u p t u o o t d l o h 0 0 2s n t s i d e m i t e l b a s i d t u p t u o 0 0 1s n t c e e m i t e s a r e p i h c / k c o l b / r e t c e s0 40 0 1s m t p p e m i t m a r g o r p e g a p25s m t w e m i t r e t s i g e r s u t a t s e t i r w0 40 0 1s m ac characteristics applicable over recommended operating range from t a = 0 c to +70 c, v cc = +2.7 v to +3.6 v c l = 1ttl gate and 30 pf (unless otherwise noted).
15 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 ac characteristics (continued) ac waveforms (1) note: 1. for spi mode 0 (0,0) output test load input test waveforms and measurement level valid in ce# v il v ih sck v ih v ih v oh v il v il v ol si so t cs t ckh t ckl t ceh t dh t ds t v t dis t oh hi-z hi-z t ch 3.3 v 1.8 k 1.3 k output pin 30 pf 3.0 v 0.0 v 1.5 v ac measurement level input
16 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 ac characteristics (continued) t hd t hd t hs t hs t hz t lz ce# sck hold# so hold timing p y tx a ms t i n us n o i t i d n o c c n i 46 f pv n i v 0 = c t u o 82 1f pv t u o v 0 = pin capacitance ( f = 1 mhz, t = 25 c ) note: these parameters are characterized but not 100% tested.
17 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 timing diagrams sck si so instruction = 0000 0110b hi-z ce# wren timing wrdi timing ce# sck si so instruction = 0000 0100b hi-z nnnnnnn 01 8 31 38 39 46 47 54 high impedance manufacture id1 device id manufacture id2 sck ce# si so instruction 9 7 1010 1011b 3 dummy bytes rdid timing
18 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 rdsr timing ce# sck si 0 12 3 56 7 8 9 10 11 12 13 14 4 instruction = 0000 0101b so 765 43 2 1 0 high impedance data out msb 0 1 2 3 5 6 7 8 9 10 11 12 13 14 4 15 765 4 32 10 data in instruction = 0000 0001b high impedance ce# sck si so wrsr timing read timing 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 36 35 37 38 ... 23 22 21 3 2 1 0 76543210 3-byte address instruction = 0000 0011b high impedance ce# sck si so
19 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 page program timing 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 2075 2076 2077 2078 2079 076 5 32 2 1 1430 23 22 21 1st byte data-in 256th byte data-in 3-byte address instruction = 0000 0010b high impedance ce# sck si so fast read timing 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 ... 23 22 21 3 2 1 0 3-byte address instruction = 0000 1011b high impedance ce# sck si so 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 765 3 0 76543210 high impedance ce# sck si so 4 1 76543210 2 data out 1 data out 2 dummy byte
20 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 block erase timing chip erase timing 01 234 567891011 28 29 30 31 0 1 2 3 21 22 23 ... 3-byte address instruction = 1101 1000b high impedance ce# sck si so 01234567 high impedance sck ce# si so instruction = 1100 0111b 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 0 1 2 3 21 22 23 ... 3-byte address instruction = 1101 0111b high impedance ce# sck si so sector erase timing
21 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 program/erase performance r e t e m a r a pt i n up y tx a ms k r a m e r e m i t e s a r e r o t c e ss m0 40 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t e s a r e k c o l bs m0 40 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t e s a r e p i h cs m0 40 0 1n o i t e l p m o c e s a r e o t d n a m m o c e s a r e g n i t i r w m o r f e m i t g n i m m a r g o r p e g a ps m25 m a r g o r p o t d n a m m o c m a r g o r p g n i t i r w m o r f n o i t e l p m o c r e t e m a r a pn i mp y tt i n ud o h t e m t s e t e c n a r u d n e0 0 0 , 0 0 1 ) 2 ( s e l c y c7 1 1 a d r a d n a t s c e d e j n o i t n e t e r a t a d0 2s r a e y3 0 1 a d r a d n a t s c e d e j l e d o m y d o b n a m u h - d s e0 0 0 , 2s t l o v4 1 1 a d r a d n a t s c e d e j l e d o m e n i h c a m - d s e0 0 2s t l o v5 1 1 a d r a d n a t s c e d e j p u - h c t a l i + 0 0 1 1 c c a m8 7 d r a d n a t s c e d e j note: these parameters are characterized and are not 100% tested. note: 1. these parameters are characterized and are not 100% tested. 2. preliminary specification only and will be formalized after cycling qualification test. reliability characteristics (1)
22 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 end view 5.00 4.80 top view side view 4.00 3.80 6.20 5.80 1.75 1.35 0.25 0.10 0.51 0.33 1.27 bsc 0.25 0.19 1.27 0.40 45 o package type informa tion ` 8s 8-pin jedec small outline integrated circuit (soic) package (measure in millimeters)
23 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 package type informa tion (continued) 8q 8-contact ulta-thin small outline no-lead (wson) package (measure in millimeters) 5.00 bsc top view side view 0.48 0.35 6.00 bsc 0.80 0.70 0.25 0.19 1.27 bsc bottom view pin 1 0.75 0.50 4.00 3.40
24 programmable microelectronics corp. issue date: december, 2003, rev: 1.3 pmc pm25lv512/010 revision hist or y e t a d. o n n o i s i v e rs e g n a h c f o n o i t p i r c s e d. o n e g a p 2 0 0 2 , r e b o t c o0 . 1c e p s y r a n i m i l e r p , n o i t a c i l b u p w e nl l a 2 0 0 2 , r e b m e c e d1 . 1e s a e l e r l a m r o fl l a 3 0 0 2 , n u j2 . 1n o i t p o e g a k c a p n o s w d e d d a3 2 , 3 , 2 , 1 3 0 0 2 , r e b m e c e d3 . 1 s n o i t p o e g a k c a p e e r f - d a e l d e d d a2 1 , 3 , 1 0 0 0 , 0 5 m o r f s e l c y c e s a r e / m a r g o r p d e e t n a r u g d e d a r g p u ) y r a n i m i l e r p ( 0 0 0 , 0 0 1 o t 1 2 , 1 n o i s n e m i d e g a k c a p d e w a r d e r d n a d e t a d p u3 2 , 2 2

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